Godwin Maben
Godwin Maben is a seasoned professional with an extensive 30-year experience in the semiconductor industry, specializing in low-power design and power optimization for System on Chip (SoC) architectures. Godwin has contributed to the development of SoCs for mobile, IoT, GPU, and networking applications, focusing on ARM and RISC-V based designs.
Godwin has a proven track record in developing the architecture of Power Management Integrated Circuits (PMIC) for mobile and IoT devices, and architecting mobile SoCs with advanced power structures, including power gating, Dynamic Voltage and Frequency Scaling (DVFS), and Multi-Voltage (MV) techniques.
In addition to optimizing logic, system, and RTL architectures to reduce power for hundreds of blocks, Godwin has extensive experience in RTL coding, specifically targeting energy efficiency for hundreds of partitions. Skilled in developing custom cells to minimize glitches and has implemented algorithms within tools to optimize power consumption.
Godwin has developed comprehensive methodologies for implementing zero-pin retention flops from pre-RTL to silicon and has architected tools such as UPF Architect. Additionally, has created higher-level abstractions to Natural Language Processing (NLP) for various tools, including HDL, SDC, and UPF.
With expertise in designing low-power circuits and HDL coding with a focus on low power, Godwin excels in power architecture, PMIC design, and debugging power issues from simulation through emulation, synthesis, place, and route (P&R), and Engineering Change Order (ECO) processes. Dedicated to advancing low-power design techniques and methodologies, ensuring the development of energy-efficient and high-performance semiconductor solutions.